1. Field of the Invention
This invention relates to a semiconductor read only memory (hereinbelow termed an "ROM"), and more particularly to an ROM in which a plurality of insulated gate field-effect transistors (hereinafter called "MISFETs") are connected in series to one output line.
2. Description of the Prior Art
In general, a circuit in which both a memory matrix and an address decoder are constructed of ROMs employs ROMs of the lateral system (ROMs in which a plurality of driving MISFETs are connected in parallel between an output terminal and a reference voltage terminal) as disclosed in `Electronics Digest` December 1973, pp. 49-50, "7. READ only MEMORY" etc.
FIG. 1 shows an address decoder, especially a word address decoder, an ROM 1, and a memory matrix ROM 2 which are formed by the above system. In the figure, the word address decoder ROM 1 decodes an encoded address signal applied from address input lines A.sub.1, A.sub.1, A.sub.2 and A.sub.2 and selects one of the word address select lines W.sub.1 -W.sub.4. The memory matrix ROM 2 is an ROM which stores 12 bits (4 words.times.3 bits). The stored contents (3 bits) of the selected column (word) in the ROM are read out from bit output lines B.sub.1 -B.sub.3.
In the memory matrix ROM 2, the selected word address select line is connected to a supply voltage V.sub.DD, whereas the non-selected word address select lines are grounded.
This means that, in the word address decoder ROM 1, current flows through all but one of the load MISFETs Q.sub.L1 -Q.sub.L4 which are connected to the word address lines W.sub.1 -W.sub.4. As a result, a large amount of power is dissipated in the word address decoder ROM 1. Where the memory capacity of the memory matrix ROM 2 is increased, the number of the non-selected word address select lines is increased accordingly, and the problem becomes more serious.
FIG. 2A shows a pattern diagram where a part of the memory matrix ROM 2 illustrated in FIG. 1 is assembled in a chip of a P-channel type MISLSI. FIG. 2B is a front sectional view along line A-A' in FIG. 2A.
In the figures, numeral 3 designates a portion formed of Si, which forms the gate electrodes of MISFETs disposed in each column and which is also the word address select line. Numeral 5 indicates a source region of each MISFET, numeral 4 a ground interconnection layer for commonly grounding the source regions 5 of the MISFETs disposed in each column, and numeral 6 a drain region of each MISFET. The ground interconnection layer 4, the source region 5 and the drain region 6 are formed of high concentration P+-type diffused layers, respectively. Numeral 7 (at the blank part inside the oblique lines of the drain region 6) denotes a contact window which is formed in an insulating layer 9 on each drain region 6, and numeral 8 is an A1 interconnection layer (corresponding to the bit output line B.sub.1 -B.sub.3) which serves to commonly connect the drain regions 6 of the MISFETs in the respective columns. The connection between the drain region 6 and the A1 interconnection layer 8 is effected through the contact window. The pattern of the ROM or the configuration of the ROM in the figures is determined by mask patterns of the diffused source and drain layers 5, 6 and the contacts 7 of the output lines 8 with the drains 6.
As is illustrated in the pattern diagram of FIG. 2A, the ROM of the lateral system has the problem that the density of integration in the MIS large-scale integrated circuit (LSI) is decreased for the following reasons:
(1) Ground interconnection layers 4 for commonly grounding the source regions of the MISFETs are required for the respective columns.
(2) Since the contact windows are formed on the drain regions 6 of the respective MISFETs, the drain regions 6 and the A1 interconnection layers 8 must be formed into large areas in consideration of mask misregistration.